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document:1g5-0126 rev.1 page 1 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram description the device is cmos dynamic ram organized as 4,194,304 words x 4 bits. it is fabricated with an advanced submicron cmos technology and designed to operate from a single 5v only or 3.3v only power supply. low voltage operation is more suitable to be used on battery backup, portable electronic application. a new refresh feature called ? self-refresh ? is supported and very slow cbr cycles are being performed. it is packaged in jedec standard 26/24 - pin plastic soj or tsop (ii). features ? single 5v (%) or 3.3v (%) only power supply ? high speed t rac access time : 50/60 ns ? low power dissipation - active mode : 5v version 605/550 mw (max.) 3.3v version 396/360 mw (max.) - standby mode : 5v version 1.375 mw (max.) 3.3v version 0.54 mw (max.) ? fast page mode access ? i/o level : ttl compatible (vcc = 5v) lvttl compatible (vcc = 3.3v) ? 2048 refresh cycles in 32 ms (std) or 128ms (s - version) ? 4 refresh mode : - ras only refresh - cas -before- ras refresh - hidden refresh - self - refresh (s - version) 10 10
document:1g5-0126 rev.1 page 2 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram pin description pin name function a0 - a10 address inputs - row address a0 - a10 - column address a0 - a10 - refresh address a0 - a10 dq1 ~ dq4 data - in/data - out ras row address strobe cas column address strobe we write enable oe output enable v cc power (+ 5v or + 3.3v) v ss ground v g 2 6 ( v ) ( s ) 1 7 4 0 0 d j dq1 we v ss dq4 a 2 a 3 v cc a 0 a 1 a 10 v cc a 8 a 7 a 6 a 5 a 4 v ss 1 2 3 4 5 6 cas oe a 9 26 25 24 23 22 21 8 9 10 11 12 13 19 18 17 16 15 14 ras dq3 nc dq2 v g 2 6 ( v ) ( s ) 1 7 4 0 0 d j dq1 we v ss dq4 a 2 a 3 v cc a 0 a 1 a 10 v cc a 8 a 7 a 6 a 5 a 4 v ss 1 2 3 4 5 6 cas oe a 9 26 25 24 23 22 21 8 9 10 11 12 13 19 18 17 16 15 14 ras dq3 nc dq2 pin configuration 26/24 - pin 300mil plastic tsop (ii) pin configuration 26/24 - pin 300mil plastic sop
document:1g5-0126 rev.1 page 3 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram we generator column- address buffers (11) refresh controller refresh counter buffers (11) address row no. 1 clock generator a0 ras a1 a2 a3 a4 a5 a6 a7 a8 control logic data - in buffer data - out buffer oe dq1 dq4 column decoder 2048 sense amplifiers i/o gating 2048 x 4 2048 x 2048 x 4 memory array 2 0 4 8 r o w d e c o d e r vcc vss block diagram cas a9 a10 no. 2 clock
document:1g5-0126 rev.1 page 4 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram truth table notes : 1. early write only. function ras cas we oe addresses dq s notes row col standby h x x x x high - z read l l h l row col data - out write : (early write) l l l x row col data - in read write l l row col data - out, data - in page - mode read 1st cycle l h l row col data - out 2st cycle l h l n/a col data - out page - mode write 1st cycle l l x row col data - in 2st cycle l l x n/a col data - in page - mode read - write 1st cycle l row col data - out, data - in 2st cycle l n/a col data - out, data - in hidden refresh read l h l row col data - out write l l x row col data - in 1 ras - only refresh l h x x row n/a high - z cbr refresh l h x x x high - z hx ? hl ? lh ? hl ? hl ? hl ? hl ? hl ? hl ? lh ? hl ? hl ? lh ? lhl ?? lhl ?? hl ?
document:1g5-0126 rev.1 page 5 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram absolute maximum rating recommended dc operating conditions capacitance ta = 25c, v cc = % or %, f = 1mhz note : 1. capacitance measured with effective capacitance measuring method. 2. cas = v ih to disable dout. parameter symbol value unit voltage on any pin relative to vss 5v 3.3v v t -1.0 to + 7.0 -0.5 to + 4.6 v supply voltage relative to vss 5v 3.3v v cc -1.0 to + 7.0 -0.5 to + 4.6 v short circuit output current i out 50 ma power dissipation p d 1.0 w operating temperature t opt 0 to + 70 c storage temperature t stg -55 to + 125 c parameter/condition symbol 5 volt version 3.3 volt version unit min typ max min typ max supply voltage v cc 4.5 5.0 5.5 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.4 - v cc + 1 . 0 2.0 - v cc + 0.3 v input low voltage, all inputs v il -1.0 - 0.8 -0.3 - 0.8 v parameter symbol typ max unit note input capacitance (address) c l1 - 5 pf 1 input capacitance ( ras , cas , oe , we ) c l2 - 7 pf 1 output capacitance (data - in, data - out) c i/o - 7 pf 1,2 5v10 3.3v10
document:1g5-0126 rev.1 page 6 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram dc characteristics; 5 - volt verion (t a = 0 to 70c , v cc = + 5v 10 %, v ss = 0v ) parameter symbol test conditions vg26 (v) (s) 17400d unit notes -5 -6 min max min max operating current i cc1 ras cycling cas cycling t rc = min. - 110 - 100 ma 1, 2 standby current low power s - version i cc2 ttl interface ras , cas = v ih dout = high - z - 2 - 2 ma cmos interface - 0.2v dout = high - z - 0.25 - 0.25 ma standard power version ttl interface ras , cas = v ih dout = high - z - 2 - 2 ma cmos interface - 0.2v dout = high - z - 1 - 1 ma ras - only refresh current i cc3 ras cycling, cas = v ih t rc = min. - 110 - 100 ma 1, 2 fast page mode current i cc4 t pc = min. - 80 - 70 ma 1,3 cas - before - ras refresh current i cc5 t rc = min. ras , cas cycling - 110 - 100 ma 1, 2 self - refresh currant (s - version) i cc8 - 350 - 350 cas - before - ras long refresh current (s - version) i cc9 standby : v cc - cas before ras refresh : 2048 cycles/128ms ras , ras : v cc - (max) dout = high - z, - 500 - 500 rascas ,v cc 3 rascas ,v cc 3 t rass 100 m s 3 m a 0.2v ras 0vv il 0.2v 0.2vv ih v ih t ras 300ns m a
document:1g5-0126 rev.1 page 7 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram dc characteristics ; 5 - volt version (cont.) (t a = 0 to 70c , v cc = + 5v 10 %, v ss = 0v ) notes : 1. l cc is specified as an average current. it depends on output loading condition and cycle rate when the device is selected. l cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. for l cc4 , address can be changed once or less within one fast page mode cycle time. parameter symbol test conditions vg26 (v) (s) 17400d unit notes -5 -6 min max min max lnput leakage current i li + 0.5v -5 5 -5 5 output leakage current i lo + 0.5v dout = disable -5 5 -5 5 output high voltage v oh l oh = -5ma 2.4 - 2.4 - v output low voltage v ol l ol = + 4.2ma - 0.4 - 0.4 v 0vvinv cc m a 0vvoutv cc m a
document:1g5-0126 rev.1 page 8 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram dc characteristics ; 3.3 - volt verion (t a = 0 to 70c , v cc = + 3.3 v 10 %, v ss = 0v ) parameter symbol test conditions vg26 (v) (s) 17400d unit notes -5 -6 min max min max operating current i cc1 ras cycling cas cycling t rc = min. - 110 - 100 ma 1, 2 standby current low power s - version i cc2 lvttl interface ras , cas = v ih dout = high - z - 0.5 - 0.5 ma cmos interface - 0.2v dout = high - z - 0.25 - 0.25 ma standard power version lvttl interface ras , cas = v ih dout = high - z - 2 - 2 ma cmos interface - 0.2v dout = high - z - 0.5 - 0.5 ma ras - only refresh current i cc3 ras cycling, cas = v ih t rc = min. - 110 - 100 ma 1, 2 fast page mode current i cc4 t pc = min. - 80 - 70 ma 1,3 cas - before - ras refresh current i cc5 t rc = min. ras , cas cycling - 110 - 100 ma 1, 2 self - refresh currant (s - version) i cc8 - 250 - 250 cas - before - ras long refresh current (s - version) i cc9 standby : v cc - cas before ras refresh : 2048 cycles/128ms ras , ras : v cc - (max) dout = high - z, - 300 - 300 rascas ,v cc 3 rascas ,v cc 3 t rass 100 m s 3 m a 0.2v ras 0vv il 0.2v 0.2vv ih v ih t ras 300ns m a
document:1g5-0126 rev.1 page 9 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram dc characteristics ; 3.3 - volt version (cont.) (t a = 0 to 70c , v cc = + 3.3 v 10 %, v ss = 0v ) notes : 1. l cc is specified as an average current. it depends on output loading condition and cycle rate when the device is selected. l cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. for l cc4 , address can be changed once or less within one fast page mode cycle time. parameter symbol test conditions vg26 (v) (s) 17400d unit notes -5 -6 min max min max input leakage current i li + 0.3v -5 5 -5 5 output leakage current i lo + 0.3v dout = disable -5 5 -5 5 output high voltage v oh l oh = -2ma 2.4 - 2.4 - v output low voltage v ol l ol = + 2ma - 0.4 - 0.4 v 0vvinv cc m a 0vvoutv cc m a
document:1g5-0126 rev.1 page 10 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ac characteristics (ta = 0 to + 70c, v cc = 5v10% or 3.3v10%, v ss = 0v) * 1, * 2, * 3, * 4 test conditions ? output load : two ttl loads and 100pf(v cc = 5.0v10%) one ttl load and 100pf(v cc = 3.3v10%) ? input timing reference levels : v ih = 2.4v, v ll = 0.8v (v cc = 5.0v10%); v ih = 2.0v, v ll = 0.8v (v cc = 3.3v10%) ? output timing reference levels : v oh = 2.0v, v ol = 0.8v (v cc = 5v10%, 3.3v10%) read, write, read - modify - write and refresh cycles (common parameters) parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max random read or write cycle time t rc 90 - 110 - ns ras precharge time t rp 30 - 40 - ns cas precharge time in normal mode t cpn 10 - 10 - ns ras pulse width t ras 50 10000 60 10000 ns 5 cas pulse width t cas 12 10000 15 10000 ns 6 row address setup time t asr 0 - 0 - ns row address hold time t rah 8 - 10 - ns column address setup time t asc 0 - 0 - ns 7 column address hold time t cah 8 - 10 - ns ras to cas delay time t rcd 12 37 14 45 ns 8 ras to column address delay time t rad 10 25 12 30 ns 9 column address to ras lead time t ral 25 - 30 - ns ras hold time t rsh 13 - 15 - ns cas hold time t csh 50 - 60 - ns cas to ras precharge time t crp 5 - 5 - ns 10 oe to din delay time t oed 12 - 15 - ns transition time (rise and fall) t t 1 50 1 50 ns 11 refresh period t ref - 32 - 32 ms refresh period (s - version) t ref - 128 - 128 ms cas to output in low-z t clz 0 - 0 - ns cas delay time from din t dzc 0 - 0 - ns oe delay time from din t dzo 0 - 0 - ns
document:1g5-0126 rev.1 page 11 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram read cycle write cycle read - modigy - write cycle parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max access time from ras t rac - 50 - 60 ns 12 access time from cas t cac - 13 - 15 ns 13,14 access time from column address t aa - 25 - 30 ns 14,15 access time from oe t oea - 13 - 15 ns read command setup time t rcs 0 - 0 - ns 7 read command hold time to cas t rch 0 - 0 - ns 10,16 read command hold time to ras t rrh 0 - 0 - ns 16 output buffer turn-off time t off 0 13 0 15 ns 17 output buffer turn-off time from oe t oez 0 13 0 15 ns 17 parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max write command setup time t wcs 0 - 0 - ns 7,18 write command hold time t wch 8 - 10 - ns write command pulse width t wp 8 - 10 - ns write command to ras lead time t rwl 13 - 15 - ns write command to cas lead time t cwl 8 - 10 - ns data-in setup time t ds 0 - 0 - ns 19 data-in hold time t dh 8 - 10 - ns 19 parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max read - modify - write cycle time t rwc 125 - 150 - ns ras to we delay time t rwd 65 - 80 - ns 18 cas to we delay time t cwd 30 - 35 - ns 18 column address to we delay time t awd 40 - 50 - ns 18 oe hold time from we t oeh 8 - 10 - ns
document:1g5-0126 rev.1 page 12 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram refresh cycle fast page mode cycle fast page mode read modify write cycle parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max cas setup time (cbr refresh) t csr 10 - 10 - ns cas hold time (cbr refresh) t chr 10 - 10 - ns 10 ras precharge to cas hold time t rpc 5 - 5 - ns 7 ras pulse width (self refresh) t rass 100 - 100 - ras precharge time (self refresh) t rps 90 - 110 - ns cas hold time (cbr self refresh) t chs -50 - -50 - ns we setup time t wsr 0 - 0 - ns we hold time t whr 10 - 10 - ns parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max fast page mode cycle time t pc 35 - 40 - ns fast page mode cas precharge time t cp 10 - 10 - ns fast page mode ras pulse width t rasp 50 10 5 60 10 5 ns 20 access time from cas precharge t cpa - 30 - 35 ns 10,14 ras hold time from cas precharge t cprh 30 - 35 - ns parameter symbol vg26 (v) (s) 17400d unit notes -5 -6 min max min max fast page mode read - modify - write cycle cas precharge to we delay time t cpw 45 - 55 - ns 11 fast page mode read - modify - write cycle time t prwc 70 - 80 - ns m s
document:1g5-0126 rev.1 page 13 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram notes : 1. ac measurements assume t t = 5ns. 2. an initial pause of 100 is required after power up, and it followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 4. all the v cc and v ss pins shall be supplied with the same voltage. 5. t ras (min) = t rwd (min) + t rwl (min) + t t in read - modify-write cycle. 6. t cas (min) = t cwd (min) + t cwl (min) + t t in read - modify-write cycle. 7 . t asc (min), t rcs (min), t wcs (min) and t rpc are determined by the falling edge of cas . 8. t rcd (max) is specified as a reference point only, and t rac (max) can be met with the t rcd (max) limit. otherwise, t rac is controlled exclusively by t cac if t rcd is greater than the specified t rcd (max) limit. 9. t rad (max) is specified as a reference point only, and t ra c (max) can be met with the t ra d (max) limit. otherwise, t ra c is controlled exclusively by t aa if t rad is greater than the specified t rad (max) limit . 10. t crp , t chr , t rch , t cpa and t cpw are determined by the rising edge of cas . 11. v ih (min) and v il (max) are reference levels for measuring timing or input signals. therefore, transition time is measured between v ih and v il . 12. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 13. assumes that t rcd t rcd (max) and t rad t rad (max). 14. access time is determined by the maximum among t aa , t cac , t cpa . 15. assumes that t rcd t rcd (max) and t rad t rad (max). 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) and t oez (max) define the time at which the output achieves the open circuit condition ( high impedance). 18. t wcs , t rwd , t cwd , and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain open circuit (high impedance) throughout the entire cycle. if t rwd t rwd (min), t cwd t cwd (min), t awd t awd (min), and t cpw t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. these parameters are referenced to cas in an early write cycle and to we edge in a delayed write or a read-modify-write cycle. 20. t rasp defines ras pulse width in fast page mode cycles. m s 3 3 3 3 3 3 3
document:1g5-0126 rev.1 page 14 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram timing waveforms ? read cycle t rc t ras t rp t crp t cpn t rrh t rch t oez t off t oea t cac t aa t rac t clz d out t rcs t asr t rah t asc t cah t rad t ral t cas t rsh t rcd t t t csh ras address dq1 ~ dq4 note : = don?t care row column cas we oe = invalid dout
document:1g5-0126 rev.1 page 15 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ?early write cycle t rc t ras t rp t wch t ds t dh t wcs t ral t cas t rsh t rcd t t t csh ras cas we dq1 ~ dq4 t crp t asr t rah t asc t cah address column row t cpn d in t rad t ral
document:1g5-0126 rev.1 page 16 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? delayed write cycle t rc t ras t rp t rwl t rcs t cas t rsh t rcd t t t csh ras cas t asr t rah t cah address column row t asc d in dq1 ~ dq4 we t crp t cpn t dh t ds t oeh t oed oe t ds open t wp t cwl
document:1g5-0126 rev.1 page 17 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? read - modify - write cycle t rwc t ras t rp t rwd t wp t rad t rwl t cas t cwl t rcd t t t cpn ras cas we t crp t asr t rah t asc t cah address column row dq1 ~ dq4 t dh t ds oe t rcs t awd t cwd d in t oed t oeh t oez t oea t cac t rac t aa dq1 ~ dq4 d out open t dzo t dzc
document:1g5-0126 rev.1 page 18 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? fast page mode read cycle t rasp t cprh t rcs t cas t rsh t rcd t oea t csh ras cas t asr t rah t cah address t cas we t crp t cp oe dq1 ~ dq4 open d out 1 t pc t cp t cas t cpn t crp t rad t cah t asc t asc t cah t asc t ral row column 1 t rrh t rch t rac t aa t aa t aa t cpa t cpa t oez t off t cac t oez t cac t cac t clz d out n we oe column 2 column n row t rp t oea t oea t clz t oez t clz d out 2 t off t off
document:1g5-0126 rev.1 page 19 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? fast page mode early write cycle t rasp t rp t wcs t cas t rsh t rcd ras cas t asr t rah t cah address t cas we t cp dq1 ~ dq4 t pc t cp t cas t cpn t crp t cah t asc t asc t cah t asc row column 1 t ds we column 2 column n t wch t wcs t wch t wcs t wch t dh t ds t dh t ds t dh d in 1 d in 2 d in n t t t csh
document:1g5-0126 rev.1 page 20 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? fast page mode delayed write cycle t rasp t cprh t rcs t cas t wp ras cas t asr t rah t cah address t cas we t rcd t rsh t cas t crp t rad t cah t asc t asc t cah t asc row column 1 t rwl t rcs t oed we oe t rp t t column n column 2 column 1 t cwl t rcs t cwl t cwl t oed t oed t oeh t oeh t oeh t ds t dh t wp t ds t dh t wp t ds t dh open open open d in 1 d in n d in 2 dq1 ~ dq4 t cp t cp t csh t pc t dzc t dzo t dzc t dzo t dzc t dzo
document:1g5-0126 rev.1 page 21 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? fast page mode read - modify - write cycle t rasp t cprh t rcs t cas t wp ras cas t asr t rah t cah address t cas we t rcd cp dq1 ~ dq4 t prwc t cp t cas t crp t rad t cah t asc t asc t cah t asc row column 1 t rwl t rcs t oed t cpa t cac we oe t rp d out 2 d out n d out 1 t t t column n column 2 column 1 t rwd t awd t cwd t cwl t rcs t cwd t awd t cpw t cwl t cpw t awd t cwd t cwl t oed t oed t oeh t oeh t oeh t cac t cac t aa t rac t oez t oea t aa t clz t oez t aa t clz t oez t ds t dh t wp t ds t dh t wp t ds t dh open open d in 1 d in n d in 2 dq1 ~ dq4 t dzc t dzc t oea t oea t cpa t oea t clz t dzc t dzo t dzo t dzo
document:1g5-0126 rev.1 page 22 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ras - only refresh cycle ras address t rc t crp t asr t rah t t t rpc row t off cas t ras t rp open t crp dq1 ~ dq4 ras t csr t wsr t rp t t t rpc t off cas t ras t rp open t crp dq1 ~ dq4 t rpc t chr t ras t rp t rc t rc t chr t csr t whr t wsr t whr we cas - before - ras refresh cycle
document:1g5-0126 rev.1 page 23 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram cbr self - refesh cycle ras we t rpc t off t csr t chs t wsr cas t rass t rps open dq1 - dq4 t whr high lmpedance
document:1g5-0126 rev.1 page 24 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ? hidden refresh cycle t rp t ras ras t rcd t crp address we t chr t cas t rsh t rah t asr t asc t cah t ral row t rch t oez cas dq1 ~ dq4 t t t rcs d t ras t ras t rp t rp t rc t rc t rc t rad t rrh t off t oea t cac t aa t rac column out oe (read) (refresh) (refresh)
document:1g5-0126 rev.1 page 25 vis vg26(v)(s)17400d 4,194,304 x 4 - bit cmos dynamic ram ordering information part number access time package vg26 (v) (s) 17400dj - 5 vg26 (v) (s) 17400dj - 6 50 ns 60 ns 300mil 26/24 - pin plastic soj ? vg ? 26 ? v ? s ? 17400 ? d ? j ?5 ? vis memory product ? technology ? 3.3v version ? self refresh ? device type and configuration ? revision ? package type (j : soj , t : tsoj ii) ? speed (5 : 50 ns, 6 : 60 ns) vg26 (v) (s) 17400dj - 5 packaging information packaging information ? 300 mil, 26/24-pin plastic soj seating plane 4-e e b b2 0.007" m c l 0.025" min. 0.004" section b-b e2 a rad r1 a1 b b d 26 21 e e1 19 14 base metal with plating c1 c b1 b 0.267 basic 0.335 basic 0.050 basic r1 e e1 e2 6.78 basic 1.27 basic 0.76 --- 7.49 7.62 1.02 0.030 7.75 0.295 17.02 b d e c1 b2 c b1 a1 a dim 0.51 0.41 0.016 8.51 basic 0.18 17.15 --- 0.66 0.18 0.41 --- --- 0.46 17.27 0.28 0.670 0.007 0.81 0.30 0.48 0.007 0.026 0.016 millimeters min. nom. 2.08 3.25 --- --- 3.51 max. min. --- 3.76 0.082 0.128 0.305 0.040 --- 0.300 0.020 0.032 0.019 0.012 0.680 0.011 0.675 --- 0.018 --- --- max. 0.148 --- nom. --- 0.138 --- inches 2. dimension d does not include mold protrusion. dimension e1 does not include interlead protrusion. mold protrusion shall not exceed 0.006"(0.15mm) per side. interlead protrusion shall not exceed 0.01"(0.25mm) per side. 1. controlling dimension : inches note: 3. dimension b2 does not include dambar protrusion or to less than 0.001"(0.025mm) below b2 min. dambar intrusion shall not reduce the shoulder width shoulder width to exceed b2 max by more than 0.005"(0.127mm) intrusion. dambar protrusion shall not cause the 1 6 8 13 a2 a2 2.54 ref. 0.100 ref.

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